1. Technical Field
The present invention relates in general to a design structure for electrical circuits and in particular to a design structure for multiplexer (MUX) circuits. Still more particularly, the present invention relates to a design structure for a configurable, low power high fan-in MUX.
2. Description of the Related Art
Multiplexer (MUX) circuits select a single output signal from multiple input signals based on one or more control signals (e.g., a decoder signal). MUX circuits thus select a single data output from multiple individual data input streams over a period of time. MUX circuits are often utilized to perform critical functions in the forwarding logic and bypassing logic of electronic circuits.
MUX circuits typically include multiple logic gates, such as NAND gates, NOR gates, and logical inverters. However, conventional MUX circuits that include static NAND and/or NOR gates include numerous interconnections and are therefore very slow and large. Conventional MUX circuits also consume large amounts of power due to the large number of connections and logic gates within the MUX circuit. Furthermore, the designs of MUX circuits that include static NAND and/or NOR gates are difficult to re-configure for different applications (i.e., they are not flexible or configurable).